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| 50 dB GSM PA Controller AD8311 FEATURES Complete RF detector/controller function >50 dB range at 0.9 GHz (-48 dBm to +3 dBm re 50 ) Accurate scaling from 0.1 GHz to 2.5 GHz Temperature-stable linear-in-dB response Log slope of 23 mV/dB, intercept at -60 dBm at 0.9 GHz True integration function in control loop Low power: 20 mW at 2.7 V Its high sensitivity allows control at low signal levels, thus reducing the amount of power that needs to be coupled to the detector. For convenience, the signal is internally ac-coupled. This high-pass coupling, with a corner at approximately 0.016 GHz, determines the lowest operating frequency. Thus, the source can be dc-grounded. The AD8311 provides a voltage output, VAPC, which has the voltage range and current drive to directly connect to the gain control pin of most handset power amplifiers. VAPC can swing from 300 mV above ground to within 200 mV below the supply voltage. Load currents of up to 6 mA can be supported. The setpoint control input is applied to pin VSET and has an operating range of 0.25 V to 1.4 V. The associated circuit determines the slope and intercept of the linear-in-dB measurement system; these are nominally 23.6 mV/dB and -59.7 dBm at 0.9 GHz. Further simplifying the application of the AD8311, the input resistance of the setpoint interface is over 35 M, and the bias current is typically 0.26 A. The AD8311 is available in a 6-ball wafer-level chip scale package (WLCSP), 1.0 mm x 1.5 mm, and consumes 7.6 mA from a 2.7 V to 5.5 V supply. APPLICATIONS Single, dual, and triple band mobile handset (GSM, DCS, EDGE) Transmitter power control GENERAL DESCRIPTION The AD8311 is a complete low cost subsystem for the precise control of RF power amplifiers operating in the frequency range 0.1 GHz to 2.5 GHz and over a typical dynamic range of 50 dB. It is intended for use in cellular handsets and other batteryoperated wireless devices. The log amp technique provides a much wider measurement range and better accuracy than controllers using diode detectors. In particular, its temperature stability is excellent over a specified range of -40C to +85C. FUNCTIONAL BLOCK DIAGRAM VPOS LOW NOISE GAIN BIAS LOW NOISE BAND GAP REFERENCE 1.35 DET RFIN 10dB 10dB 10dB 10dB V OFFSET COMPENSATION COMM INTERCEPT POSITIONING I DET DET DET DET HI-Z LOW NOISE RAIL-TO-RAIL BUFFER FLTR VSET 23mV/dB 250mV TO 1.4V = 50dB VAPC Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved. 05545-001 AD8311 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 11 Basic Theory................................................................................ 11 Controller-Mode Log Amps ..................................................... 12 Control Loop Dynamics............................................................ 12 Basic Connections ...................................................................... 14 Range on VSET and RFIN......................................................... 14 Transient Response..................................................................... 15 Mobile Handset Power Control Example ............................... 15 Power-On and Power-Off ......................................................... 16 Input Coupling Options ............................................................ 16 Temperature Drift ...................................................................... 17 Device Calibration and Error Calculation.............................. 17 Selecting Calibration Points to Improve Accuracy over a Reduced Range ........................................................................... 18 Device Handling......................................................................... 19 Evaluation Board ............................................................................ 20 Outline Dimensions ....................................................................... 22 Ordering Guide .......................................................................... 22 REVISION HISTORY 6/05--Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD8311 SPECIFICATIONS VPOS = 2.7 V, Frequency = 0.1 GHz, TA = 25C, 52.3 termination on RFIN, light condition = 600 lux, unless otherwise noted. Table 1. Parameter SPECIFIED FREQUENCY RANGE MEASUREMENT MODE1 (f = 0.1 GHz) Input Impedance 1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope2 Intercept2 VSET Voltage--High Power In VSET Voltage--Low Power In Temperature Sensitivity Conditions RFIN (Pin 6) No termination resistor on RFIN TA = +25C -40C < TA < +85C 1 dB error 1 dB error Min 0.1 Typ Max 2.5 Unit GHz || pF dB dB dBm dBm mV/dB dBm V V dB/C dB/C || pF dB dB dBm dBm mV/dB dBm V V dB/C dB/C || pF dB dB dBm dBm mV/dB dBm V V dB/C dB/C +2 21.5 -66 PIN = -10 dBm PIN = -40 dBm PIN = -10 dBm 25C TA +85C -40C TA +25C No termination resistor on RFIN TA = +25C -40C < TA < +85C 1 dB error 1 dB error 2140 || 1.97 47 46 +2.6 -44.5 23.8 -58.9 1.16 0.45 -0.0020 +0.0121 370 || 1.58 51 50 +2.8 -47.9 23.6 -59.7 1.17 0.46 0.0015 0.0094 180 || 1.67 42 41 -5.6 -48.0 22.7 -60.8 1.15 0.47 0.0056 0.0077 -44 25.5 -51 MEASUREMENT MODE (f = 0.9 GHz) Input Impedance 1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope2 Intercept2 VSET Voltage--High Power In VSET Voltage--Low Power In Temperature Sensitivity PIN = -10 dBm PIN = -40 dBm PIN = -10 dBm 25C TA +85C -40C TA +25C No termination resistor on RFIN TA = +25C -40C < TA < +85C 1 dB error 1 dB error MEASUREMENT MODE (f = 1.9 GHz) Input Impedance 1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope2 Intercept2 VSET Voltage--High Power In VSET Voltage--Low Power In Temperature Sensitivity PIN = -10 dBm PIN = -40 dBm PIN = -10 dBm 25C TA +85C -40C TA +25C Rev. 0 | Page 3 of 24 AD8311 Parameter MEASUREMENT MODE (f = 2.5 GHz) Input Impedance 1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope2 Intercept2 VSET Voltage--High Power In VSET Voltage--Low Power In Temperature Sensitivity Conditions No termination resistor on RFIN TA = +25C -40C < TA < +85C 1 dB error 1 dB error Min Typ 164 || 1.55 42 41 -6.2 -47.7 22.5 -60.6 1.14 0.46 -0.0004 +0.0090 0.2 2.3 2.4 2.54 0.3 0.4 2.55 2.65 Max Unit || pF dB dB dBm dBm mV/dB dBm V V dB/C dB/C V V V V V mA/A nV/Hz MHz ns ns V/s ns V V dB/mV A M V/s 5.5 10.7 12.9 10 2000 V mA mA s ns OUTPUT INTERFACE Minimum Output Voltage Maximum Output Voltage vs. Temperature General Limit Output Current Drive Output Noise Small Signal Bandwidth Fall Time Rise Time Slew Rate Response Time VSET INTERFACE Nominal Input Range Logarithmic Scale Factor Bias Current Source Input Resistance Slew Rate POWER INTERFACE Supply Voltage Quiescent Current vs. Temperature Power-On Time Power-Off Time 1 2 PIN = -10 dBm PIN = -40 dBm PIN = -10 dBm 25C TA 85C -40C TA +25C VAPC (Pin 2) VSET 150mV IOUT = 3 mA RL = 85C, VPOS = 3 V, IOUT = 6 mA 2.7 V VPOS 5.5 V, RL = VSET = 1.5 V, RFIN = -50 dBm, source/sink RF Input = 2 GHz, 0 dBm, fNOISE = 100 kHz, CFLT = 220 pF RFIN = -10 dBm; from FLTR to VAPC Input level = off to 0 dBm, 90% to 10% Input level = 0 dBm to off, 10% to 90% 90% - 10%, VSET = 0.3 V, open loop FLTR = Open VSET (Pin 3) RFIN = 0 dBm; measurement mode RFIN = -50 dBm; measurement mode RFIN = -10 dBm; VSET = 1.4 V VPOS - 0.1 5/200 170 30 120 270 15 130 1.4 0.27 0.04 0.26 36 14 2.7 5 VPOS (Pin 1) 7.6 8.2 3 100 -40C TA +85C Time from VPOS high to VAPC within 1% of final value, VSET 200 mV Time from VPOS low to VAPC within 1% of final value, VSET 200 mV VAPC (Pin 2) to VSET (Pin 3) with inversion stage, sinusoidal input signal. Mean and standard deviation specifications are available in Table 4. Rev. 0 | Page 4 of 24 AD8311 ABSOLUTE MAXIMUM RATINGS Table 2. Parameters Supply Voltage VPOS VAPC, VSET RFIN Equivalent Voltage Internal Power Dissipation JA (WLCSP) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Ratings 5.5 V 0 V, VPOS 17 dBm 1.6 V rms 60 mW 200C/W 125C -40C to +85C -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 24 AD8311 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BUMP 1 INDICATOR VPOS 1 6 RFIN VAPC 2 5 COMM VSET 3 4 FLTR 05545-002 TOP VIEW Not to Scale Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3 4 5 6 Mnemonic VPOS VAPC VSET FLTR COMM RFIN Function Positive Supply Voltage: 2.7 V to 5.5 V. Output. Control voltage for gain control element. Setpoint Input. Nominal input range 0.25 V to 1.4 V. Integrator Capacitor. Connect between FLTR and COMM. Device Common (Ground). RF Input. Rev. 0 | Page 6 of 24 AD8311 TYPICAL PERFORMANCE CHARACTERISTICS VPOS = 2.7 V; TA = 25C; CFLT = open; light condition = 600 lux, 52.3 termination; unless otherwise noted. Colors: +25C = black, -40C = blue, +85C = red. 10 0.9GHz 1.9GHz 2.5GHz 0.1GHz -10 4 0 3 2 ERROR (dB) RF INPUT AMPLITUDE (dBm) 1.9GHz 2.5GHz -20 1 0.1GHz 0.9GHz -30 -40 0 -1 -60 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 -3 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VSET (V) VSET (V) Figure 3. Input Amplitude vs. VSET 10 +25C -40C 0 3 4 Figure 6. Log Conformance vs. VSET 10 +25C -40C +85C -10 2 ERROR (dB) ERROR (dB) 05545-022 05545-021 4 0 RF INPUT AMPLITUDE (dBm) 3 RF INPUT AMPLITUDE (dBm) +85C -10 2 ERROR (dB) -20 1 -20 1 -30 -40 0 -1 -30 +85C -40 -40C 0 -1 +85C ERROR AT +85C AND -40C BASED ON DEVIATION FROM SLOPE AND INTERCEPT AT +25C 0.4 0.6 0.8 1.0 -40C +25C -50 -60 0.2 -2 05545-018 -50 -60 0.2 1.2 1.4 -3 1.6 ERROR AT +85C AND -40C BASED ON DEVIATION FROM SLOPE AND INTERCEPT AT +25C 0.4 0.6 0.8 1.0 -2 +25C 1.2 1.4 -3 1.6 VSET (V) VSET (V) Figure 4. Input Amplitude and Log Conformance vs. VSET at 0.1 GHz -40C, +25C, and +85C 10 +25C -40C +85C -10 +85C -20 1 2 ERROR (dB) Figure 7. Input Amplitude and Log Conformance vs. VSET at 1.9 GHz -40C, +25C, and +85C 10 +25C -40C +85C -10 -20 2 1 4 4 0 RF INPUT AMPLITUDE (dBm) 3 RF INPUT AMPLITUDE (dBm) 0 3 -30 0 -30 0 -40 ERROR AT +85C AND -40C BASED ON DEVIATION FROM SLOPE AND INTERCEPT AT +25C 0.4 0.6 0.8 1.0 -40C +25C -1 -40 +25C -40C +85C ERROR AT +85C AND -40C BASED ON DEVIATION FROM SLOPE AND INTERCEPT AT +25C 0.4 0.6 0.8 1.0 1.2 1.4 VSET (V) -1 -50 -60 0.2 -2 05545-019 -50 -60 0.2 -2 -3 1.6 1.2 1.4 -3 1.6 VSET (V) Figure 5. Input Amplitude and Log Conformance vs. VSET at 0.9 GHz -40C, +25C, and +85C Rev. 0 | Page 7 of 24 Figure 8. Input Amplitude and Log Conformance vs. VSET at 2.5 GHz -40C, +25C, and +85C 05545-020 05545-017 -50 -2 AD8311 3 3 2 2 +85C 1 1 ERROR (dB) 0 ERROR (dB) +85C 0 -1 +25C -2 05545-023 -1 +25C -2 -40C 05545-026 -40C -3 -60 -3 -60 -50 -40 -30 -20 -10 0 10 -50 -40 -30 -20 -10 0 10 RF INPUT AMPLITUDE (dBm) RF INPUT AMPLITUDE (dBm) Figure 9. Distribution of Error over Temperature After Ambient Normalization vs. Input Amplitude at 0.1 GHz 3 Figure 12. Distribution of Error over Temperature After Ambient Normalization vs. Input Amplitude at 1.9 GHz 3 2 +85C 2 +85C 1 1 ERROR (dB) 0 ERROR (dB) +25C 0 -1 -1 +25C -2 05545-024 -2 -40C -3 -60 -40C -3 -60 -50 -40 -30 -20 -10 0 10 -50 -40 -30 -20 -10 0 10 RF INPUT AMPLITUDE (dBm) RF INPUT AMPLITUDE (dBm) Figure 10. Distribution of Error over Temperature after Ambient Normalization vs. Input Amplitude at 0.9 GHz Figure 13. Distribution of Error over Temperature after Ambient Normalization vs. Input Amplitude at 2.5 GHz 3.5 3.3 3.1 0mA VAPC (V) 2.9 2mA 2.7 6mA 2.5 05545-025 100MHz 4mA 900MHz 2.5GHz 1.9GHz 2.8 2.9 3.0 3.1 VPOS (V) 3.2 3.3 3.4 3.5 START FREQUENCY = 0.05GHz STOP FREQUENCY = 3.5GHz Figure 11. Maximum VAPC Voltage vs. Supply Voltage by Load Current Figure 14. Input Impedance vs. Frequency, No Termination Resistor on RFIN Rev. 0 | Page 8 of 24 05545-028 2.3 2.7 05545-027 AD8311 VAPC VAPC GND 200mV PER VERTICAL DIVISION 1V PER VERTICAL DIVISION GND VPOS 1V PER VERTICAL DIVISION 2s PER HORIZONTAL DIVISION 05545-029 RF INPUT GND PULSED RF 0.1GHz, 0dBm 100ns PER HORIZONTAL DIVISION Figure 15. Power-On and -Off Response with VSET Grounded 10MHz REF R AND S SMT03 OUTPUT SIGNAL GENERATOR RF OUT AD811 49.9 732 52.3 2 3 Figure 18. VAPC Response Time, Full-Scale Amplitude Change, Open-Loop R AND S SMT03 SIGNAL GENERATOR PULSE MODULATION MODE RF OUT RF SPLITTER -3dB 2.7V 0.1F 1 2 EXT TRIG STANFORD DS345 PULSE GENERATOR TRIG OUT 10MHz REF OUTPUT PULSE MODE IN EXT TRIG OUT PULSE OUT PICOSECOND PULSE LABS PULSE GENERATOR TRIG OUT AD8311 1 -3dB VPOS VAPC VSET RFIN 6 COMM 5 AD8311 VPOS VAPC VSET RFIN 6 52.3 COMM 5 FLTR 4 NC FLTR 4 220pF TRIG TEK P6205 FET PROBE TEK P6205 FET PROBE TEK TDS694C SCOPE 0.3V 3 TRIG TEK TDS694C SCOPE NC = NO CONNECT 05545-030 Figure 16. Test Setup for Power-On and -Off Response with VSET Grounded 45 40 35 30 25 20 15 10 5 0 -5 -10 -15 -20 -25 -30 -35 -40 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 Figure 19. Test Setup for VAPC Response Time 10k CFLT = 220pF, RF INPUT = 2GHz CFLT = 0pF NOISE SPECTRAL DENSITY (nV/ Hz) -50dBm 1k -40dBm 0dBm -20dBm 100 -38dBm -10dBm -35dBm -30dBm CFLT = 220pF PHASE (Degrees) AMPLITUDE (dB) 05545-039 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 17. AC Response from VSET to VAPC Figure 20. VAPC Noise Spectral Density Rev. 0 | Page 9 of 24 05545-034 05545-033 TEK P6205 FET PROBE 05545-032 GND AD8311 25 -55 -57 23 -40C 23 INTERCEPT (dBm) SLOPE (mV/dB) -59 +25C +25C -61 -40C +85C -63 22 +85C 05545-035 21 0 0.5 1.0 1.5 2.0 2.5 FREQUENCY (GHz) -65 0 0.5 1.0 1.5 2.0 2.5 FREQUENCY (GHz) Figure 21. Slope vs. Frequency -40C, +25C, and +85C 25 -58 Figure 23. Intercept vs. Frequency -40C, +25C, and +85C -59 23 SLOPE (mV/dB) 0.1GHz INTERCEPT (dBm) 0.1GHz 0.9GHz -60 1.9GHz -61 2.5GHz 0.9GHz 23 1.9GHz 2.5GHz 22 -62 05545-036 05545-038 21 2.5 3.0 3.5 4.0 VPOS (V) 4.5 5.0 5.5 -63 2.5 3.0 3.5 4.0 VPOS (V) 4.5 5.0 5.5 Figure 22. Slope vs. Supply Voltage Figure 24. Intercept vs. Supply Voltage Table 4. Typical Specifications at Selected Frequencies at 25C (Mean and Sigma) Slope (mV/dB) Mean Sigma 23.8 0.1 23.6 0.1 22.7 0.1 22.5 0.1 Intercept (dBm) Mean Sigma -58.9 0.4 -59.7 0.4 -60.8 0.5 -60.6 0.5 1 dB Dynamic Range Low Point (dBm) High Point (dBm) Mean Sigma Mean Sigma -44.5 0.8 +2.6 0.3 -47.9 0.3 +2.8 0.1 -48.0 0.6 -5.6 0.6 -47.7 0.6 -6.2 0.5 Frequency (GHz) 0.1 0.9 1.9 2.5 Rev. 0 | Page 10 of 24 05545-037 AD8311 THEORY OF OPERATION The AD8311 is a wideband logarithmic amplifier (log amp) similar in design to the AD8313, AD8314, and AD8315. Like the AD8315, it is strictly optimized for use in power control applications rather than as a measurement device. Figure 25 shows the main features in block schematic form. The output (Pin 2, VAPC) is intended to be applied directly to the automatic power-control (APC) pin of a power amplifier module. corresponds to 20 dB, VSLP/20 represents the volts/dB. For the AD8311, a nominal (low frequency) slope of 24 mV/dB was chosen, and the intercept VZ was placed at -59 dBm for a sine wave input (251 V rms). However, both the slope and the intercept are dependent on frequency. Keeping in mind that log amps do not respond to power but only to voltages and that the calibration of the intercept is waveform dependent and is only quoted for a sine wave signal, the equivalent power response can be written as BASIC THEORY Logarithmic amplifiers provide a type of compression in which a signal having a large range of amplitudes is converted to one of a smaller range. The use of the logarithmic function uniquely results in the output representing the decibel value of the input. The fundamental mathematical form is VOUT = VDB (PIN - PZ ) (2) VOUT = VSLP log 10 where: VIN VZ (1) where the input power PIN and the equivalent intercept PZ are both expressed in dBm (thus, the quantity in parentheses is simply a number of decibels), and VDB is the slope expressed in mV/dB. For a log amp having a slope VDB of 24 mV/dB and an intercept at -59 dBm, the output voltage for an input power of - 30 dBm is 0.024 [-30 - (-57)] = 0.696 V. Further details about the structure and function of log amps can be found in data sheets for other log amps produced by Analog Devices. Refer to the data sheets for the AD640 and AD8307, both of which include a detailed discussion of the basic principles of operation and explain why the intercept depends on waveform, an important consideration when complex modulation is imposed on an RF carrier. VIN is the input voltage. VZ is called the intercept (voltage) because when VIN = VZ the argument of the logarithm is unity and thus the result is zero. VSLP is called the slope (voltage), which is the amount by which the output changes for a certain change in the ratio (VIN/VZ). When BASE-10 logarithms are used, denoted by the function log10, VSLP represents the volts/decade, and since a decade (PRECISE GAIN CONTROL) VPOS LOW NOISE GAIN BIAS (PRECISE SLOPE CONTROL) LOW NOISE BAND GAP REFERENCE (CURRENT-MODE SIGNAL) 1.35 VAPC DET RFIN 10dB DET DET DET DET HI-Z LOW NOISE RAIL-TO-RAIL BUFFER 10dB 10dB 10dB (CURRENTNULLING MODE) INTERCEPT POSITIONING (CURRENT-MODE FEEDBACK) V (SMALL INTERNAL FILTER CAPACITOR FOR GHz RIPPLE) I FLTR VSET 23mV/dB 250mV TO 1.4V = 50dB COM (WEAK GM STAGE) Figure 25. Block Schematic Rev. 0 | Page 11 of 24 05545-003 OFFSET COMPENSATION AD8311 The intercept need not correspond to a physically realizable part of the signal range for the log amp. Thus, the specified intercept is -58.9 dBm at 0.1 GHz, whereas the smallest input for accurate measurement (a +1 dB error) at this frequency is higher, about -44.5 dBm. At 2.5 GHz, the +1 dB error point shifts to -47.7 dBm. This positioning of the intercept is deliberate and ensures that the VSET voltage is within the capabilities of certain digital-to-analog converters (DACs), whose outputs cannot swing below 200 mV. Figure 26 shows the 100 MHz response of the AD8311; the vertical axis represents not the output (at the VAPC pin) but the value required at the power control pin (VSET) to null the control loop. This is explained in the Controller-Mode Log Amps section. 1.5 In a device intended for measurement applications, this current would then be converted to an equivalent voltage, to provide the log(VIN) function shown in Equation 1. However, the design of the AD8311 differs from standard practice in that its output needs to be a low noise control voltage for an RF power amplifier, not a direct measure of the input level. Further, it is highly desirable that this voltage be proportional to the timeintegral of the error between the actual input VIN and a dc voltage VSET (applied to Pin 3, VSET). VSET defines the setpoint, a target value for the power level typically generated by a DAC. This is achieved by converting the difference between the sum of the detector outputs (still in current form) and an internally generated current proportional to VSET to a single-sided current-mode signal. This, in turn, is converted to a voltage (at Pin 4, FLTR, the low-pass filter capacitor node) to provide a close approximation to an exact integration of the error between the power present in the termination at the input of the AD8311 and the setpoint voltage. Finally, the voltage developed across the ground-referenced filter capacitor CFLT is buffered by a special low noise amplifier of low voltage gain (x1.35) and presented at Pin 2 (VAPC) for use as the control voltage for the RF power amplifier. This buffer can provide rail-to-rail swings and can drive a substantial load current, including large capacitors. Note that the RF power amplifier is assumed to have a positive slope with RF power increasing monotonically with an increasing APC control voltage. 1.211V @ -8dBm 1.0 VSET (V) SLOPE = 23.8mV/dB ACTUAL 0.5 448mV @ -40dBm IDEAL 0 100V 1mV -67dBm -47dBm -58.9dBm 10mV -27dBm VIN, PIN 100mV -7dBm 1V (RMS) 13dBm (RE 50) 05545-040 CONTROL LOOP DYNAMICS In order to understand how the AD8311 behaves in a complete control loop, an expression for the current in the integration capacitor as a function of the input PIN and the setpoint voltage VSET must be developed. Refer to Figure 27. Figure 26. Basic Calibration of the AD8311 at 0.1 GHz CONTROLLER-MODE LOG AMPS The AD8311 combines the two key functions required for the measurement and control of the power level over a moderately wide dynamic range. First, it provides the amplification needed to respond to small signals in a chain of four amplifier/limiter cells (see Figure 25), each having a small signal gain of 10 dB and a bandwidth of approximately 3.5 GHz. At the output of each of these amplifier stages is a full-wave rectifier, essentially a square law detector cell that converts the RF signal voltages to a fluctuating current having an average value that increases with signal level. A further passive detector stage is added before the first stage. These five detectors are separated by 10 dB, spanning some 50 dB of dynamic range. Their outputs are each in the form of a differential current, making summation a simple matter. It is readily shown that the summed output can closely approximate a logarithmic function. The log conformance error, which is the overall accuracy at the extremes of this total range viewed as the deviation from an ideal logarithmic response, can be judged by reference to Figure 6, which shows that errors across the central 40 dB are moderate. DIRECTIONAL COUPLER POUT RF PA PCW RF DRIVE: UP TO 2.5GHz IDET = ISLP PIN + IINT RFIN 6 VIN LOGARITHMIC RF DETECTION SUBSYSTEM IDET FLTR 4 IERR CFLT VSET 3 SETPOINT VSET INTERFACE ISET = VSET/RSET 05545-047 VAPC 1.35 2 Figure 27. Behavioral Model of the AD8311 Rev. 0 | Page 12 of 24 AD8311 First, the summed detector currents are written as a function of the input power. Equation 6 can be restated as I DET = I SLP x PIN + I INT where: (3) V APC ( s ) = where: VSET - VSLP x PIN - V INT sT (7) IDET is the partially filtered demodulated signal, whose steadystate average value is extracted through the subsequent integration step. ISLP is the slope, which has a value of 5.75 A/dB. PIN is the input power in dBm (assuming 50 input match). IINT is the current intercept which, as previously noted, is dependent on the RF waveform (not the envelope). Assuming a sinusoidal input, IINT is 350 A. The current generated by the setpoint interface is simply VSLP is ISLP x RSET, which has a value of 24 mV/dB. VINT is the voltage intercept given by IINT x RSET, which has a value of 1.44 V. T is the effective time constant for the integration and is equal to RSET x CFLT/1.35. The factor of 1.35 arises because of the voltage gain of the buffer. So the open-loop integration time constant can be written as TOpenLoop = RSET x CFLT 1.35 (8) I SET = VSET RSET (4) where the RSET resistor is 4.1 k. The difference between this current and IDET is applied to the loop filter capacitor CFLT. At this point note that the inclusion of a filter resistor, RFLT, can be helpful in improving the phase margin at low powers where the PA control gain (that is, POUT/VAPC) is large, as is described later in this section. For now assume that RFLT is zero. It follows that the voltage appearing on this capacitor, VFLT, is the timeintegral of the difference current. To assess the closed-loop performance, refer to the block diagram in Figure 28 and calculate the loop transfer function. In general, the buffer time constant (BUFFER) and the log amp time constant (LOGAMP) can be neglected, except in the case of very high PA control function gains (> than 500 dB/V) and/or very wide PA control port bandwidths. Assuming that the frequency response of the output buffer and the log amp can be neglected, the overall transfer function can be expressed as VFLT (s ) = (I SET - I DET ) sC FLT POUT = I SET + I SLP x 30 - I INT x 1.35 x (G PA (1 + s PA )) x (1 sC FLT ) [ (5) (6) 1 + I SLP x 1.35 x (G PA (1 + s PA )) sC FLT [ ] ] (9) = VSET RSET - I SLP x PIN - I INT sC FLT Here, GPA is the PA control function gain POUT/VAPC given in dB/V, and the factor of -30 is due to the coupler. The input power to the log amp, PIN, is given in dBm and therefore is simply POUT of the PA minus the coupler value, typically -30 dB, or PIN = POUT - 30. Equation 9 assumes that the next parasitic pole in the control loop comes from the PA. For a typical PA, a 1 MHz pole is not unusual, making this a good assumption. Therefore, except for in the case of a very wide bandwidth on the PA control port (>10 MHz), the response time and stability of the control loop is mainly determined by the characteristics of the PA. This is true for both the gain and the phase response. It is essential to understand both the magnitude and frequency response of the power amplifier control port. POUT The control output VAPC is slightly greater than this, since the gain of the output buffer is x1.35, plus a slight offset voltage. The polarity is such that VAPC rises to its maximum value for any value of VSET greater than the equivalent value of PIN. That is, the AD8311 seeks to drive the RF power to its maximum value whenever it falls below the setpoint. The use of exact integration results in a dc error that is theoretically zero, and the logarithmic detection law would ideally result in a constant response time following a step change of either the setpoint or the power level if the power-amplifier control function were likewise linear-in-dB. This latter condition is rarely true, however, and it follows that in practice the loop response time depends on the power level. This effect can strongly influence the design of the control loop. ISET IERR 1 + RFLT sCFLT VFLT + _ IDET 1.35 1 + s BUFFER VAPC GPA (dB/V) 1 + sPA 1 + sLOGAMP Figure 28. Control Loop Block Diagram Rev. 0 | Page 13 of 24 05545-048 ISLP PIN + IINT PIN -30dB COUPLER AD8311 Continuing with the stability analysis, the gain of the control loop can be expressed as DIRECTIONAL COUPLER POWER AMP GAIN CONTROL VOLTAGE VAPC RFIN POUT I SET where: = k 1 + kA (10) ATTENUATOR AD8311 RFIN VSET FLTR 05545-008 DAC k= 1.35 x G PA x (1 sC FLT ) 1 + s PA (dB/A) (11) (12) 52.3 CFLT RFLT A = I SLP (A/dB) Figure 30. Typical Application The effect of the zero resistor, RFLT, can be easily included by replacing (1/sCFLT) with (RFLT + 1/sCFLT). The criteria for loop stability can be derived by setting the denominator of Equation 10 equal to 0, giving 0 = 1+ (1 + s PA ) x sC FLT (G PA x I SLP ) 1.35 x (1 + sR FLT C FLT ) (13) From Equation 13, the closed-loop integration time constant is given by TClosedLoop = C FLT (GPA x I SLP x 1.35 ) In a power control loop, the AD8311 provides both the detector and controller functions. A sample of the power amplifier's (PA) output power is coupled to the RF input of the AD8311, usually via a directional coupler. In dual mode applications, where there are two PAs and two directional couplers, the outputs of the directional couplers can be passively combined (both PAs will never be turned on simultaneously) before being applied to the AD8311. A setpoint voltage is applied to VSET from the controlling source (generally this is a DAC). Any imbalance between the RF input level and the level corresponding to the setpoint voltage is corrected by the AD8311's VAPC output that drives the gain control terminal of the PA. This restores a balance between the actual power level sensed at the input of the AD8311 and the value determined by the setpoint. This assumes that the gain control sense of the variable gain element is positive, that is, an increasing voltage from VAPC tends to increase gain. VAPC can swing from 200 mV to within 100 mV of the supply rail and can source up to 6 mA. If the control input of the PA needs to source current, a suitable load resistor can be connected between VAPC and COMM. The output swing and current sourcing capability of VAPC is shown in Figure 11. (14) The gain and phase margins of the control loop can be deduced from the Bode plots of Equation 13. BASIC CONNECTIONS Figure 29 shows the basic connections for operating the AD8311, and Figure 30 shows a block diagram of a typical application. The AD8311 is typically used in the RF power control loop of a mobile handset. A supply voltage of 2.7 V to 5.5 V is required for the AD8311. The supply to the VPOS pin should be decoupled with a low inductance 0.1 F surface-mount ceramic capacitor, close to the device. The AD8311 has an internal input coupling capacitor, which negates the need for external ac-coupling. This capacitor, along with the low frequency input impedance of the device of approximately 2.14 k, sets the minimum usable input frequency to around 0.016 GHz. A broadband 50 input match is achieved in this example by connecting a 52.3 resistor between RFIN and ground. A Smith chart plot of input impedance vs. frequency is shown in Figure 14. Other coupling methods are also possible (see the Input Coupling Options section). C1 0.1F RANGE ON VSET AND RFIN The relationship between the RF input level and the setpoint voltage follows from the nominal transfer function of the device (see Figure 4, Figure 5, Figure 7, and Figure 8). At 0.9 GHz, for example, a voltage of 1 V on VSET indicates a demand for -18 dBm at RFIN. The corresponding power level at the output of the power amplifier is greater than this amount due to the attenuation through the directional coupler. For setpoint voltages of less than approximately 150 mV, VAPC unconditionally remains at its minimum level of approximately 300 mV. This feature can be used to prevent any spurious emissions during power-up and power-down phases. Above 250 mV, VSET has a linear control range up to 1.4 V, corresponding to a dynamic range of 50 dB. This results in a slope of 23.8 mV/dB, or approximately 42.0 dB/V. AD8311 R1 52.3 RFIN 1 VPOS +VS (2.7V TO 5.5V) 2 VAPC VAPC RFIN 6 COMM 5 CFLT Figure 29. Basic Connections Rev. 0 | Page 14 of 24 05545-007 VSET 3 VSET FLTR 4 AD8311 TRANSIENT RESPONSE The time domain response of power amplifier control loops, using any kind of controller, is only partially determined by the choice of filter. In the case of the AD8311, the filter has a true integrator form 1/sT as shown in Equation 7, with a time constant given by Equation 8. The large signal step response is also strongly dependent on the form of the gain-control law. Nevertheless, some simple rules can be applied. When the filter capacitor CFLT is very large it dominates the time domain response, but the incremental bandwidth of this loop still varies as VAPC traverses the nonlinear gain-control function of the PA. This bandwidth is highest at the point where the slope of the tangent drawn on the PA power-control curve is greatest--that is, for power outputs near the center of the PA's range--and is much reduced at both the minimum and the maximum power levels, where the slope of the gain control curve is lowest due to its S-shaped form. Using smaller values of CFLT, the loop bandwidth generally increases in inverse proportion to its value. Eventually, however, a secondary effect appears due to the inherent phase lag in the power amplifier's control path, some of which can be due to parasitic or deliberately added capacitance at the VAPC pin. This 3.5V 4.7 F 4.7 F results in the characteristic poles in the ac loop equation moving off the real axis and thus becoming complex (and somewhat resonant). This is a classic aspect of control loop design. The lowest permissible value of CFLT needs to be determined experimentally for a particular amplifier. For GSM and DCS power amplifiers, CFLT typically ranges from 150 pF to 300 pF. In many cases, some improvement in the worst-case response time can be achieved by including a small resistor in series with CFLT; this generates an additional zero in the closed-loop transfer function, which serves to cancel a higher order pole in the overall loop. A more complex filter network can be used to minimize the settling time of the loop--for example, a combination of the main capacitor, CFLT, shunted by a second capacitor and resistor series. MOBILE HANDSET POWER CONTROL EXAMPLE Figure 31 shows a complete power amplifier control circuit for a dual mode handset. The PF08123B (Hitachi), a dual mode (GSM, DCS) PA, is driven by a nominal power level of +3 dBm. The PA has a single gain control line; the band to be used is selected by applying either 0 V or 2 V to the PA's VCTL input. F1000pF p0001 BAND SELECT 0V/+2V 1000pF PIN GSM 3dBm VCTL PF08123B POUT GSM 35dBm MAX LDC15D190A0007A 1 7 8 5 6 2 OT TO ANTENNA 49.9 4 3 PIN DCS 3dBm VAPC POUT DCS 32dBm MAX 500 (OPTIONAL, SEE TEXT) 0.1F +VS 2.7V R21 600 R31 1k 1R2, ATTN 20dB AD8311 RFIN 6 COMM 5 FLTR 4 R1 52.3 1 2 VPOS VAPC VSET 8-BIT RAMP DAC 0V-2.55V 3 150pF 1.5k R3 OPTIONAL, SEE TEXT 05545-049 Figure 31. Dual Mode (GSM/DCS) PA Control Example Rev. 0 | Page 15 of 24 AD8311 Some of the output power from the PA is coupled off using a dual-band directional coupler (Murata part number LDC15D190A0007A). This has a coupling factor of approximately +19 dB for the GSM band and +14 dB for DCS and an insertion loss of 0.38 dB and 0.45 dB, respectively. Because the PF08107B transmits a maximum power level of +35 dBm for GSM and +32 dBm for DCS, additional attenuation of 20 dB is required before the coupled signal is applied to the AD8311. This results in peak input levels to the AD8311 of -4 dBm (GSM) and -2 dBm (DCS). While the AD8311 gives a linear response for input levels up to +2 dBm, for highly temperature-stable performance at maximum PA output power the maximum input level should be limited to approximately -2 dBm (see Figure 5 and Figure 7). This does, however, reduce the sensitivity of the circuit at the low end. The operational setpoint voltage, in the range 250 mV to 1.4 V, is applied to the VSET pin of the AD8311. This typically is supplied by a DAC. The AD8311's VAPC output drives the level control pin of the power amplifier directly. VAPC reaches a maximum value of approximately 2.5 V on a 2.7 V supply while delivering the 3 mA required by the level control input of the PA. This is more than sufficient to exercise the gain control range of the PA. During initialization and completion of the transmit sequence, VAPC should be held at its minimum level of 300 mV by keeping VSET below 150 mV. In this example, VSET is supplied by an 8-bit DAC that has an output range from 0 V to 2.55 V or 10 mV per bit. This sets the control resolution of VSET to 0.4 dB/bit (0.04 dB/mV times 10 mV). If finer resolution is required, the DAC's output voltage can be scaled using two resistors as shown. This converts the DAC's maximum voltage of 2.55 V down to 1.6 V and increases the control resolution to 0.25 dB/bit. A filter capacitor (CFLT) must be used to stabilize the loop. The choice of CFLT depends to a large degree on the gain control dynamics of the power amplifier, something that is frequently poorly characterized, so some trial and error might be necessary. In this example, a 150 pF capacitor is used and a 1.5 k series resistor is included. This adds a zero to the control loop and increases the phase margin, which helps to make the step response of the circuit more stable when the PA output power is low and the slope of the PA's power control function is the steepest. A smaller filter capacitor can be used by inserting a series resistor between VAPC and the control input of the PA. A series resistor works with the input impedance of the PA to create a resistor divider, which reduces the loop gain. The size of the resistor divider ratio depends on the available output swing of VAPC and the required control voltage on the PA. This technique can also be used to limit the control voltage in situations where the PA cannot deliver the power level being demanded by VAPC. Overdrive of the control input of some PAs causes increased distortion. It should be noted, however, that if the control loop opens (that is, VAPC goes to its maximum value in an effort to balance the loop), the quiescent current of the AD8311 increases somewhat, particularly at supply voltages greater than 3 V. Figure 32 shows the relationship between VSET and output power (POUT) at 0.9 GHz. The overall gain control function is linear in dB for a dynamic range of over 40 dB. Note that for VSET voltages below 300 mV, the output power drops off steeply as VAPC drops toward its minimum level of 300 mV. 40 -40C 30 +85C 2 3 OUTPUT POWER (dBm) 20 1 10 -40C +25C +85C 0 0 -1 -10 +25C -2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 SETPOINT VOLTAGE (V) Figure 32. POUT vs. VSET at 0.9 GHz for Dual Mode Handset Power Amplifier Application; -40C, +25C, and +85C POWER-ON AND POWER-OFF The AD8311 can be completely disabled by pulling the supply voltage to ground. The voltage on VSET should be kept below 150 mV during power-on and power-off to prevent any unwanted transients on VAPC. INPUT COUPLING OPTIONS The internal 5 pF coupling capacitor of the AD8311 and the low frequency input impedance of 2.14 k give a high-pass input corner frequency of approximately 16 MHz. This sets the minimum operating frequency. Figure 33, Figure 34, and Figure 35 shows three options for input coupling. A broadband resistive match can be implemented by connecting a shunt resistor to ground at RFIN (Figure 33). This 52.3 resistor (other values can also be used to select different overall input impedances) combines with the input impedance of the AD8311 to give a broadband input impedance of 50 . While the input resistance and capacitance (CIN and RIN) of the AD8311 vary from device to device by approximately 20%, as well as in the same device over a range of frequencies (Figure 14), the dominance of the external shunt resistor means that the variation in the overall input impedance is close to the Rev. 0 | Page 16 of 24 05545-041 -20 -3 1.6 ERROR (dB) AD8311 tolerance of the external resistor. This method of matching is most useful in wideband applications or in multiband systems where there is more than one operating frequency. A reactive match can also be implemented as shown in Figure 34. This is not recommended at low frequencies because device tolerances dramatically vary the quality of the match due to the large input resistance. For low frequencies, Figure 33 or Figure 35 is recommended. In Figure 34, the matching components are drawn as generic reactances. Depending on the frequency, the input impedance, and the availability of standard value components either a capacitor or an inductor is used. As in the previous case, the input impedance at a particular frequency is plotted on a Smith Chart and matching components are chosen (shunt or series L, shunt or series C) to move the impedance to the center of the chart. AD8311 RFIN RSHUNT 52.3 CC TEMPERATURE DRIFT Figure 36 shows the log slope and error over temperature for a 0.9 GHz input signal. Error due to drift over temperature consistently remains within 1 dB and only begins to exceed this limit when the ambient temperature goes above +65 C and below -20 C. For all frequencies using a reduced temperature range, higher measurement accuracy is achievable. 10 -40C -20C 0C +25C +45C +65C +85C 4 3 0 -10 PIN (dBm) 2 1 0 -1 -2 ERROR (dB) ERROR (dB) 05545-043 -20 -30 -40 -50 -60 0.2 0.4 0.6 0.8 1.0 1.2 1.4 CIN RIN 05545-009 VSET (V) Figure 36. Typical Drift at 900 GHz for Various Temperatures DEVICE CALIBRATION AND ERROR CALCULATION The measured transfer function of the AD8311 at 0.9 GHz is shown in Figure 37. The figure shows plots of both input power and calculated error vs. setpoint voltage. The vertical axis represents the input power required at the RFIN pin to null the control loop when a VSET voltage is applied. As the setpoint voltage varies from about 0.2 V to 1.5 V, the corresponding input power varies from -60 dBm to +10 dBm. Figure 33. Broadband Resistive Input Coupling Option AD8311 x1 x2 RFIN CC CIN RIN 05545-010 Figure 34. Narrow Band Reactive Input Coupling Option 10 PINIDEAL = (VSET1/ SLOPE) + INTERCEPT ERROR (dB) = (PINIDEAL - PIN) SLOPE = (VSET2 - VSET1)/(PIN1 - PIN2) INTERCEPT = PIN1 - (VSET1 / SLOPE) 4 ANTENNA 0 3 -40C AD8311 RFIN (dBm) STRIPLINE RATTN RFIN CC -10 +85C -20 PIN2 +25C +85C 2 1 0 VSET2 -40C CIN RIN 05545-011 -30 PA -40 PIN1 INTERCEPT VSET1 +25C -1 -2 Figure 35. Series Attention Input Coupling Option -50 Figure 35 shows a third method for coupling the input signal into the AD8311. A series resistor connected to the RF source combines with the input impedance of the AD8311 to resistively divide the input signal being applied to the input. This has the advantage of very little power being tapped off in RF power transmission applications. -60 0 0.2 0.4 0.6 0.8 VSET (V) 1.0 1.2 1.4 -3 1.6 Figure 37. Transfer Function of AD8311 at 0.9 GHz Because slope and intercept vary from device to device, boardlevel calibration must be performed to achieve high accuracy. Rev. 0 | Page 17 of 24 05545-042 -3 1.6 AD8311 In a control loop, calibration is performed by applying two levels to the AD8311's setpoint voltage and measuring the corresponding power. The calibration points are generally chosen to be within the linear-in-dB operating range of the device (see Figure 37). Calculation of slope and intercept is done using the equations 10 0 -10 RFIN (dBm) +85C +25C -40C 4 PIN2 VSET2 3 -40C 2 1 ERROR (dB) ERROR (dB) 05545-045 05545-044 PIN1 VSET1 +85C +25C -20 SLOPE = (VSET 2 - VSET 1 ) /(PIN 2 - PIN 1 ) INTERCEPT = PIN 1 - (VSET 1 / SLOPE ) (15) (16) -30 0 -1 -2 -40 Once slope and intercept have been calculated, an equation can be written which allows calculation of an (unknown) power based on the setpoint voltage. PIN = (V SET / SLOPE ) + INTERCEPT -50 -60 0 0.2 0.4 0.6 0.8 VSET (V) 1.0 1.2 1.4 -3 1.6 (17) Figure 38. Output Voltage and Error vs. PIN with 2-Point Calibration at Approximately 0.975 V and 1.3 V Using Equation 17 as a reference for the ideal input power, the log conformance error of the measured data can be calculated: ERROR(dB) = (PIN,IDEAL - PIN,MEASURED ) (18) Calibration points should be chosen to suit the application at hand. In general, though, the calibration points should never be chosen in the nonlinear portion of the log amp's transfer function (above 1.4 V or below 0.35 V in this case). Figure 39 shows how calibration points can be adjusted to increase dynamic range, but at the expense of linearity. In this case the calibration points for slope and intercept are set at 0.37 V and 1.37 V. These points are at the end of the device's linear range. Once again at 25C we see an error of 0 dB at the calibration points. Note also that the range over which the AD8311 maintains an error of less than 0.5 dB is extended to more than 45 dB at 25C and more than 40 dB over temperature. The disadvantage of this approach is that linearity suffers, especially in the middle of the range. 10 +85C +25C -40C 4 PIN2 VSET2 Figure 37 includes a plot of the error at 25C, the temperature at which the AD8311 is calibrated. Note that the error is not zero. This is because the AD8311 does not perfectly follow the ideal VSET vs. PIN equation, even within its operating region. The error at the calibration points (0.45 V and 1.15 V in this case) is, however, equal to zero by definition. Figure 37 also includes error plots for the output voltage at -40C and +85 C. These error plots are calculated using the slope and intercept at +25C. This is consistent with calibration in a mass-production environment where calibration at temperature is not practical. SELECTING CALIBRATION POINTS TO IMPROVE ACCURACY OVER A REDUCED RANGE RFIN (dBm) 0 -10 3 In some applications very high accuracy is required at just one power level or over a reduced input range. For example, in a wireless transmitter, the accuracy of the high power amplifier (HPA) is most critical at or close to full power. Figure 38 shows the same measured data as Figure 37. Notice that accuracy is very high from -15 dBm to 0 dBm. Below -15 dBm the error increases to about -2 dB. This is because the calibration points have been changed to approximately 0.975 V and 1.3 V. 2 1 -20 -40C -30 +25C -40 PIN1 VSET1 +85C 0 -1 -2 -50 -60 0 0.2 0.4 0.6 0.8 VSET (V) 1.0 1.2 1.4 -3 1.6 Figure 39. Dynamic Range Extension by Choosing Calibration Points that are Close to the End of the AD8311's Linear Range Rev. 0 | Page 18 of 24 AD8311 Another way of presenting the error function of a log amp detector is shown in Figure 40. In this case, the dB error at hot and cold temperatures is calculated with respect to the transfer function at ambient. This is a key difference in comparison to the previous plots. Up to now, all errors have been calculated with respect to the ideal transfer function at ambient. When we use this alternative technique, the error at ambient becomes by definition equal to 0 (see Figure 40). This would be valid if the device transfer function perfectly followed the ideal PIN = VSET / SLOPE + INTERCEPT equation. However since a log amp in practice never perfectly follows this equation (especially outside of its linear operating range), this plot tends to artificially improve linearity and extend the dynamic range. This plot is a useful tool for estimating temperature drift at a particular power level with respect to the (nonideal) response at ambient. However, achieving this level of accuracy in an end application requires calibration at multiple points in the device's operating range. 10 0 -10 +85C -20 -40C 1 0 -1 -2 DOES NOT TAKE INTO ACCOUNT TRANSFER FUNCTIONS' NONLINEARITIES AT +25C 0 0.2 0.4 0.6 0.8 VSET (V) 1.0 1.2 1.4 05545-046 +85C +25C -40C 4 3 2 ERROR (dB) RFIN (dBm) -30 +25C -40 -50 -60 -3 1.6 Figure 40. Error vs. Temperature with respect to Output Voltage at 25 C DEVICE HANDLING The wafer-level chip scale package consists of solder bumps connected to the active side of the die. The part is lead-free with 95.5% tin, 4.0% silver, and 0.5% copper solder bump composition. The WLCSP package can be mounted on printed circuit boards using standard surface-mount assembly techniques; however, caution should be taken to avoid damaging the die. See the AN-617 application note for additional information. WLCSP devices are bumped die, and exposed die can be sensitive to light condition, which can influence specified limits. Rev. 0 | Page 19 of 24 AD8311 EVALUATION BOARD Figure 41 shows the schematic of the AD8311 WLCSP evaluation board. The layout and silkscreen of the component and circuit sides are shown in Figure 42 to Figure 45. The board is powered by a single supply in the range 2.7 V to 5.5 V. The power supply is decoupled by a 0.1 F capacitor. A 100 pF capacitor provides additional supply decoupling, but is not necessary for basic operation. Table 5 details the various configuration options of the evaluation board. For operation in controller mode, both jumpers J1 and J2 should be removed. The setpoint voltage is applied to VSET, RFIN is connected to the RF source (PA output or directional coupler), and VAPC is connected to the gain control pin of the PA. When used in controller mode, a capacitor must be installed in C4 for loop stability (R2 must also be installed, 0 by default). For GSM/DCS handset power amplifiers, this capacitor should typically range from 150 pF to 300 pF. A quasi-measurement mode (where the AD8311 delivers an output voltage that is proportional to the log of the input signal) can be implemented, to establish the relationship between VSET and RFIN, by installing the two jumpers J1 and J2. This mimics an AGC loop. To establish the transfer function of the log amp, the RF input should be swept while the voltage on VSET is measured, that is, the SMA connector labeled VSET now acts as an output. This is the simplest method to validate operation of the evaluation board. When operated in this mode, a large capacitor (0.01 F or greater) must be installed in C4 (filter capacitor) to ensure loop stability. The op amp must be powered with a nominal voltage of 2.7 V to 5.5 V with the VS supply. Alternately, J3 can be installed to power the op amp with the AD8311's VPOS power supply. C1 0.1F VPOS R3 VAPC C3 (OPEN) 0 R4 (OPEN) C2 100pF 1 52.3 AD8311 VPOS VAPC VSET RFIN 6 COMM 5 FTLR 4 R1 RFIN 2 3 C4 (OPEN) VSET VPOS J2 C6 0.1F R6 10k R7 16.2k J1 J3 VS C5 0.1F R2 0 R10 (OPEN) R8 17.8k R5 10k C7 (OPEN) R9 (OPEN) TO EDGE CONNECTOR 05545-012 TO EDGE CONNECTOR Figure 41. Evaluation Board Schematic Rev. 0 | Page 20 of 24 AD8311 05545-013 Figure 42. Layout of Component Side (WLCSP) Figure 44. Silkscreen of Component Side (WLCSP) 05545-013 Figure 45. Silkscreen of Circuit Side (WLCSP) Figure 43. Layout of Circuit Side (WLCSP) Table 5. Evaluation Board Configuration Options Component VPOS, GND R1 Function Supply and Ground Vector Pins. Input Interface. The 52.3 resistor in Position R1 combines with the AD8311's internal input impedance to give a broadband input impedance of around 50 . Note that the AD8311's RF input is internally ac-coupled. Output Interface. R4 and C3 can be used to check the response of VAPC to capacitive and resistive loading. R3/R4 can be used to reduce the slope of VAPC. Power Supply Decoupling. The nominal supply decoupling consists of a 0.1 F capacitor at C1. C2 can be used for additional supply decoupling. Filter Capacitor. The response time of VAPC can be modified by placing a capacitor between FLTR (Pin 4) and ground. The control loop phase margin can be increased by adding a series resistor. Measurement Mode. A quasi-measurement mode can be implemented by installing J1 and J2 (connecting an inverted VAPC to VSET) to yield the nominal relationship between RFIN and VSET. In this mode, a large capacitor (0.01 F or greater) must be installed in C4. J3 can be installed to power the op-amp with the VPOS power supply. Alternately, the op-amp can be powered with the VS supply pin. Alternate Interface. R5 and R6 allow for VOUT and VSET to be accessible from the edge connector, which is only used for characterization. Default Condition Not Applicable R1 = 52.3 (Size 0402) R3, R4, C3 C1, C2 C4, R2 R3 = 0 (Size 0402) R4 = C3 = open (Size 0402) C1 = 0.1 F (Size 0402) C2 = 100 pF (Size 0402) C4 = open (Size 0402) R2 = 0 (Size 0402) J1, J2 = installed J3 = installed J1, J2, J3 R9, R10 R9 = R10 = open (Size 0402) Rev. 0 | Page 21 of 24 05545-016 05545-015 AD8311 OUTLINE DIMENSIONS 1.00 0.95 0.90 A1 BALL CORNER 1.50 1.45 1.40 0.380 0.355 0.330 0.675 0.595 0.515 SEATING PLANE B A 1 0.345 0.295 0.245 1.00 BSC 2 0.50 BSC 3 TOP VIEW (BUMP SIDE DOWN) 0.270 0.240 0.210 0.075 COPLANARITY 0.50 BSC BOTTOM VIEW (BUMP SIDE UP) Figure 46. 6-Ball Wafer Level Chip Scale Package [WLCSP] (CB-6) Dimensions shown in millimeters ORDERING GUIDE Model AD8311ACBZ-P71 AD8311ACBZ-P21 AD8311-EVAL 1 Temperature Range -40C to +85C -40C to +85C Package Description 6-Ball Wafer Level Chip Scale Package [WLCSP], 7" Pocket Tape and Reel 6-Ball Wafer Level Chip Scale Package [WLCSP], 7" Pocket Tape and Reel Evaluation Board Package Option CB-6 CB-6 Branding Q04 Q04 Ordering Quantity 3000 250 Z = Pb-free part. Rev. 0 | Page 22 of 24 AD8311 NOTES Rev. 0 | Page 23 of 24 AD8311 NOTES (c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05545-0-6/05(0) Rev. 0 | Page 24 of 24 |
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